Differential operational amplifier and bandgap reference voltage generating circuit

ABSTRACT

A differential operational amplifier, which comprises: a voltage adjusting module, coupled between a first predetermined voltage source and a second predetermined voltage source, for adjusting a first voltage via a first voltage adjusting value to generate a first adjusted voltage, and for adjusting a second voltage via a second voltage adjusting value to generate a second adjusted voltage, wherein the first voltage adjusting value and the second voltage adjusting value change corresponding to a temperature; and a differential signal computing module, coupled between the first predetermined voltage source and the second predetermined voltage source, for generating an output voltage according the first adjusted voltage and the second adjusted voltage.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a differential operational amplifier and a bandgap reference voltage generating circuit applying the differential operational amplifier, and particularly relates to a differential operational amplifier that can reduce the temperature for the input voltage and a bandgap reference voltage generating circuit applying the differential operational amplifier.

2. Description of the Prior Art

In the field of circuit design, a reference voltage generating circuit is always applied to generate an accurate reference voltage as a voltage standard for other devices. Voltage generating circuits can be classified to various kinds, and one of them is a bandgap reference voltage generating circuit. The devices inside such circuit adjusts the voltage or the current thereof responding to a temperature coefficient, such that the generated reference voltage can be kept at a stable value.

The bandgap reference voltage generating circuit always comprises a differential operational amplifier to control the operation for the bandgap reference voltage generating circuit via a first voltage and a second voltage. The first voltage and the second voltage change corresponding to a temperature difference. The differential operational amplifier always comprise the NMOSFET input pair or the PMOSFET input pair illustrated in FIG. 1 to receive above-mentioned first voltage and second voltage. Either the first voltage V₁ or the second voltage V₂ has a negative correlation with a temperature. Therefore, if the differential operational amplifier operates at a lower operational voltage V_(DD) and operates at a low temperature, the voltage difference V_(DD) between a source terminal and a drain terminal for the PMOSFET P_(a) of the PMOSFET input pair is suppressed (as shown in FIG. 2), such that the PMOSFET P_(a) operates in a linear region thus the differential operational amplifier comprises a smaller amplifier gain. On the opposite, if the differential operational amplifier operates at a high temperature, the voltage difference V_(DS) between a source terminal and a drain terminal for the NMOSFET N_(a) of the NMOSFET input pair is suppressed, such that the NMOSFET N_(a) operates in a linear region thus the differential operational amplifier comprises a smaller amplifier gain.

In the above-mentioned case, the V_(GS) (the voltage difference between the gate terminal and the source terminal) must be increased, if the PMOSFET P_(a) or the NMOSFET N_(a) need constant output currents. However, the difference between the first voltage V₁ and the second voltage V₂ change (as shown in FIG. 3) if the V_(GS) increases, thereby the reference voltage generated by the reference voltage generating circuit is also affected.

SUMMARY OF THE INVENTION

One objective of the present invention is to provide a differential operational amplifier that can decrease the level that the input changes due to the temperature.

Another objective of the present invention is to provide a differential operational amplifier that can decrease the level that the input changes due to the temperature.

One embodiment of the present invention discloses a differential operational amplifier, which comprises: a voltage adjusting module, coupled between a first predetermined voltage source and a second predetermined voltage source, for adjusting a first voltage via a first voltage adjusting value to generate a first adjusted voltage, and for adjusting a second voltage via a second voltage adjusting value to generate a second adjusted voltage, wherein the first voltage adjusting value and the second voltage adjusting value change corresponding to a temperature; and a differential signal computing module, coupled between the first predetermined voltage source and the second predetermined voltage source, for generating an output voltage according the first adjusted voltage and the second adjusted voltage.

Another embodiment of the present invention discloses a bandgap reference voltage generating circuit, which comprises a current mirror, a differential operational amplifier, a voltage generating module and a reference voltage resistance device. The current mirror generates a first current at a first current output terminal, for generating a second current at a second current output terminal, and for generating a third current at a third current output terminal, wherein the second current maps from the first current and the third current maps from the first current or the second current. The differential operational amplifier comprises: an operational output terminal; a first operational input terminal; a second operational input terminal; a voltage adjusting module, coupled between a first predetermined voltage source and a second predetermined voltage source, for adjusting a first voltage via a first voltage adjusting value to generate a first adjusted voltage, and for adjusting a second voltage via a second voltage adjusting value to generate a second adjusted voltage, wherein the first voltage adjusting value and the second voltage adjusting value change corresponding to a temperature; and a differential signal computing module, coupled between the first predetermined voltage source and the second predetermined voltage source, for generating a control voltage according the first adjusted voltage and the second adjusted voltage.

The voltage generating module, generates a first voltage at the first operational input terminal according to the first current, and for generating a second voltage at the second operational input terminal according to the second current, wherein the differential operational amplifier generates the control signal to the current mirror according to the first voltage and the second voltage, to control the first current, the second current and the third current; and a reference voltage resistance device, comprising a first terminal receiving the third current and a second terminal coupled to the second voltage source, wherein the third current generates a reference voltage at the first terminal of the reference voltage resistance device.

In view of above-mentioned description, the present invention adjusts the first and the second input voltages via at least one adjusting amount changing corresponding to the temperature variation. Thereby the firs input voltage and the second input voltage have less difference corresponding to the temperature variation, thus the suppressing for the V_(DS) of the transistor in the differential operational amplifier decreases. By this way, the differential operational amplifier can have a better performance, and the bandgap reference voltage generating circuit applying the differential operational amplifier can generate a more stable reference voltage.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating a differential operational amplifier for a prior art bandgap reference voltage generating circuit.

FIG. 2 is a schematic diagram illustrating a relation between a temperature and a PMOSFET's V_(DS) for a prior art differential operational amplifier.

FIG. 3 is a schematic diagram illustrating a situation that a difference between the first voltage and the second voltage changes corresponding to the temperature variation, for prior art.

FIG. 4 is a block diagram illustrating a differential operational amplifier, according to one embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a differential operational amplifier, according to one embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a differential operational amplifier, according to another embodiment of the present invention.

FIG. 7 is a schematic diagram illustrating a relation between a temperature and a PMOSFET's V_(DS) for a differential operational amplifier according to the present invention.

FIG. 8 is circuit diagram illustrating a bandgap reference voltage generating circuit applying the differential operational amplifier according to the present invention.

FIG. 9 is a schematic diagram illustrating a comparison between the bandgap reference voltage generating circuit of the present invention and the bandgap reference voltage generating circuit for prior art.

DETAILED DESCRIPTION

FIG. 4 is a block diagram illustrating a differential operational amplifier 400, according to one embodiment of the present invention. As shown in FIG. 4, the differential operational amplifier 400 comprises a voltage adjusting module 401 and a differential signal computing module 403. The voltage adjusting module 401 is coupled between a first predetermined voltage source and a second predetermined voltage source (V_(DD) and GND, not illustrated in FIG. 4), for adjusting a first voltage V₁ via a first voltage adjusting value to generate a first adjusted voltage V_(1a), and for adjusting a second voltage V₂ via a second voltage adjusting value to generate a second adjusted voltage V_(2a). The first voltage adjusting value and the second voltage adjusting value change corresponding to a temperature. The differential signal computing module 403 is coupled between the first predetermined voltage source and the second predetermined voltage source, for generating an output voltage V_(out) according the first adjusted voltage V_(1a) and the second adjusted voltage V_(2a) at an output terminal T_(o).

FIG. 5 is a circuit diagram illustrating a differential operational amplifier, according to one embodiment of the present invention. However, please note, the circuit diagram in FIG. 5 is only for example and does not mean to limit the present invention. As shown in FIG. 5, the voltage adjusting module 401 comprises: a first NMOSFET N₁, comprising: a drain terminal coupled to the first predetermined voltage source V_(DD), a gate terminal receiving the first voltage V₁, a source terminal outputting the first adjusted voltage V_(1a). The first voltage adjusting value is a voltage difference V_(GS1) between the gate terminal of the first NMOSFET N₁ and the source terminal of the first NMOSFET N₁. Additionally, the voltage adjusting module 401 comprises a second NMOSFET N₂, comprising: a drain terminal coupled to the first predetermined voltage source V_(DD), a gate terminal receiving the second voltage V₂, a source terminal outputting the second adjusted voltage V_(2a). The second voltage adjusting value is a voltage difference V_(GS2) between the gate terminal of the second NMOSFET N₂ and the source terminal of the second NMOSFET N₂. Please note, the first NMOSFET N₁ and second NMOSFET N₂ can be replaced by other transistors.

The differential signal operating module 403 comprises: a first PMOSFET P₁, a second PMOSFET P₂, a third PMOSFET P₃, a fourth PMOSFET P₄, a third NMOSFET N₃, a fourth NMOSFET N₄ and a fifth NMOSFET N₅. The first PMOSFET P₁ comprises a gate terminal receiving the first adjusted voltage V_(1a). The second PMOSFET P₂ comprises: a gate terminal receiving the second adjusted voltage V_(2a), and a source terminal coupled to a source terminal of the first PMOSFET P₁. The third PMOSFET P₃ comprises: a source terminal coupled to a first predetermined voltage source V_(DD), and a drain terminal coupled to the source terminal of the first PMOSFET P₁ and the second PMOSFET P₂. The fourth PMOSFET P₄ comprises: a source terminal coupled to the first predetermined voltage source V_(DD), a gate terminal coupled to the gate terminal of the third PMOSFET, and a drain terminal coupled to the gate terminal of the third PMOSFET P₃ and an output terminal T_(o). The third NMOSFET N₃ comprises: a drain terminal coupled to the drain terminal of the second PMOSFET P₂ and a gate terminal of the third NMOSFET N₃, and a source terminal coupled to the second predetermined voltage source GND. The fourth NMOSFET N₄ comprises: a drain terminal coupled to a drain terminal of the first PMOSFET P₁, a source terminal coupled to the second predetermined voltage source GND, and a gate terminal coupled to a base of the third NMOSFET N₃. The fifth NMOSFET N₅, comprises: a drain terminal coupled to the output terminal T_(o), a gate terminal coupled to the drain terminal of the fourth NMOSFET N₄, and a source terminal coupled to the second predetermined voltage source GND.

The structure for the differential signal computing module 403 in FIG. 5 is a two stage CMOS differential operational amplifier, wherein the first PMOSFET P₁, the second PMOSFET P₂, the third PMOSFET P₃, the third NMOSFET N₃ and the fourth NMOSFET N₄ are included in the first stage, and the fourth PMOSFET P₄, the fifth NMOSFET N₅ are included in the second stage. The third PMOSFET P₃ provides a biasing voltage to the first stage amplifier, the first PMOSFET P₁ and the second PMOSFET P₂ form a differential input pair. Additionally, the third NMOSFET N₃ and the fourth NMOSFET N₄ are arranged to provide active loading and to implement a single end output transforming for the circuit. The second stage amplifier is a common source amplifier. The fourth PMOSFET P₄ is arranged to provide a bias voltage and for active loading.

In one embodiment, the first NMOSFET N₁, the second NMOSFET N₂, the third NMOSFET N₃, the fourth NMOSFET N₄, the fifth NMOSFET N₅, the sixth NMOSFET N₆, the seventh NMOSFET N₇ and the eighth NMOSFET N₈ operate at a 1.2 v. Also, the first PMOSFET P₁, the second PMOSFET P₂ operate at 1.2 v, and the third PMOSFET P₃, the fourth PMOSFET P₄, the fifth PMOSFET P₅ operate at 3.3 v. However, it is not limited.

As above-mentioned, the first voltage V₁ and the second voltage V₂ have a negative correlation for the temperature, thus increase while the temperature decreasing. In the embodiments, the voltage output at the output terminal T_(o) is generated according to the first adjusted voltage V_(1a) and the second adjusted voltage V_(2a). Comparing with the first voltage V₁ and the second voltage V₂, the first adjusted voltage V_(1a) and the second adjusted voltage V_(2a) respectively minuses V_(GS1) and V_(GS2) for the first NMOSFET N₁ and the second NMOSFET N₂, which increase corresponding to the decreasing of the temperature. Therefore, the amount that the first adjusted voltage V_(1a) and the second adjusted voltage V_(2a) increase corresponding to the temperature decreases, as shown in FIG. 7 of the present invention. Accordingly, the output voltage generated at the output terminal T_(o) can suffer less disturbance from the temperature.

The differential operational amplifier can further comprise other devices. For example, the differential operational amplifier 400 further comprises a sixth NMOSFET N₆ and a seventh NMOSFET N₇. The sixth NMOSFET N₆ comprises: a drain terminal coupled to the source terminal of the first NMOSFET N₁, and a source terminal coupled to the second voltage source GND. The seventh NMOSFET N₇ comprises: a drain terminal coupled to the source terminal of the second NMOSFET N₂, a source terminal coupled to second predetermined voltage source GND, and a base coupled to a gate terminal of the sixth NMOSFET N₆. The sixth NMOSFET N₆ and the seventh NMOSFET N₇ are arranged to be an equivalent resistor, to help the first NMOSFET N₁, the second NMOSFET N₂ generate currents. Additionally, the differential operational amplifier 400 further comprise a fifth PMOSFET P5 and an eighth NMOSFET N₈, which are applied as a buffer. The fifth PMOSFET P₅ comprises: a source terminal coupled to the first predetermined voltage source V_(DD), a gate terminal coupled to a base of the fourth PMOSFET P₄. The eighth NMOSFET N₈ comprises: a drain terminal coupled to a drain terminal of the fifth PMOSFET and a gate terminal of the eighth NMOSFET, a source terminal coupled to the second predetermined voltage source GND.

The voltage adjusting module and the differential signal computing module provided by the present invention can further comprise other devices besides the devices in FIG. 5. FIG. 6 is a circuit diagram illustrating a differential operational amplifier, according to another embodiment of the present invention. As shown in FIG. 6, the voltage adjusting module 601 further comprises a first native NMOSFET N_(a1) and a second native NMOSFET N_(a2) besides the first NMOSFET N₁ and the second NMOSFET N₂. The first native NMOSFET N_(a1) comprises: a drain terminal coupled to the first predetermined voltage source V_(DD), a gate terminal coupled to the gate terminal of the first NMOSFET N₁, and a source terminal coupled to the drain terminal of the first NMOSFET N₁. The second native NMOSFET N_(a2) comprises: a drain terminal coupled to the first predetermined voltage source V_(DD), a gate terminal coupled to the gate terminal of the second NMOSFET N₂, and a source terminal coupled to the drain terminal of the second NMOSFET N₂. Since the conductive voltage for the native NMOSFETs, thus the first native NMOSFET N_(a1) and the second native NMOSFET N_(a2) can make sure the VDS for the first NMOSFET N₁ and the second NMOSFET N₂ is not over the breaking voltage. The differential signal computing module 603 further comprises a third native NMOSFET N_(a3), which comprises: a drain terminal coupled to the drain terminal of the fourth PMOSFET P₄, a gate terminal coupled to the gate terminal of the fifth NMOSFET N₅, and a source terminal coupled to the drain terminal of the fifth NMOSFET N₅. Similarly, while operating at a high voltage environment, the third native NMOSFET N_(a3) can make sure that the V_(DS) of the fifth NMOSFET N₅ is not over the breaking voltage. In one embodiment, the first native NMOSFET N_(a1), the second native NMOSFET N_(a2), and the third native NMOSFET N_(a3) all operate at a 3.3 v.

FIG. 8 is circuit diagram illustrating a bandgap reference voltage generating circuit applying the differential operational amplifier according to the present invention. As shown in FIG. 8, the bandgap reference voltage generating circuit 800 comprises a current mirror 801, a differential operational amplifier OP, an input voltage generating module 803 and a reference voltage resistance device R_(r). The current mirror 801 receives a first predetermined voltage V_(DD) and generates a first current I₁ at a first current output terminal T_(c1), generates a second current I₂ at a second current output terminal T_(c2), and generates a third current I₃ at a third current output terminal T_(c3). The second current I₂ maps from the first current I₁, and the third current I₃ maps from the first current I₁ or the second current I₂. The differential operational amplifier comprises: an operational output terminal T_(o1), a first operational input terminal T₁₁ and a second operational input terminal T₁₂. The input voltage adjusting module 803 generates a first voltage V₁ at the first operational input terminal T₁₁ according to the first current I₁, and generates a second voltage V₂ at the second operational input terminal T₁₂ according to the second current I₂. The differential operational amplifier OP generates a control voltage V_(c) at the operational output terminal T_(o1) according to the first voltage V₁ and the second voltage V₂ (i.e. the output voltage V_(out) in FIG. 4) to the current mirror 801 to control the first current I₁, the second current I₂ and the third current I₃. In the following embodiment, the first voltage V₁ and the second voltage V₂ are the same due to the virtual short of the differential operational amplifier OP, thus the first current I₁ and the second current I₂ are the same. Additionally, the third current I₃ maps from the second current I₂ and is the same as the second current I₂, but not limited. A reference voltage V_(r) is generated while the third current I₃ flowing through the reference voltage resistance device R_(r). Furthermore, the differential operational amplifier OP can comprise the circuits as above-mentioned description.

In one embodiment, the current mirror 801 comprises a PMOSFET P_(o), the PMOSFET P_(Q) and the PMOSFET P_(R). The PMOSFET P_(o) comprises: a source terminal coupled to the first predetermined voltage V_(DD), a drain terminal as the first current output terminal T_(c1), and a gate terminal receiving the control voltage V_(c). The PMOSFET P_(Q) comprises: a source terminal coupled to the first predetermined voltage V_(DD), a drain terminal as the second current output terminal T_(c2), and a gate terminal receiving the control voltage V_(c). The PMOSFET P_(R) comprises: a source terminal coupled to the first predetermined voltage V_(DD), a drain terminal as the third current output terminal T_(c2), and a gate terminal coupled to a base of the PMOSFET P_(Q).

In one embodiment, the input voltage generating module 803 comprises: a first resistance device R₁, a second resistance device R₂, a third resistance device R₃, a first BJT Q₁ and a second BJT Q₂. The first terminal of the resistance device R₁ is coupled to the first operational input terminal T_(I1). The collecting terminal of the first BJT Q₁ is coupled to a second terminal of the first resistance device R₁, and the emitting terminal of the first BJT Q₁ is coupled to a second predetermined voltage GND. The second resistor R₂ comprises a first terminal coupled to the first operational input terminal T_(I1), and a second terminal coupled to a second predetermined voltage GND. The second BJT Q₂ comprises: a collecting terminal coupled to the second operational input terminal T_(I2), an emitting terminal coupled to the second predetermined voltage GND, and a basic terminal coupled to a basic terminal of the first BJT Q₁ and coupled to the second predetermined voltage GND. The third resistance device R₃ comprises: a first terminal coupled to the second operational input terminal T_(I2), and a second terminal coupled to the second predetermined voltage GND.

The operation for the embodiment of FIG. 8 is illustrated as below. In the following embodiment, the resistance values of the second resistance device R₂ and the third resistance device R₃ are assumed to be the same, and a size of the second BJT Q₂ is X times for the first BJT Q₁. As above-mentioned, the first voltage V₁ and the second voltage V₂ are the same due to the virtual short of the differential operational amplifier OP. The currents flowing through the second resistance device R₂ and the third resistance device R₃ are the same since the second resistance device R₂ and the third resistance device R₃ have the same resistance values. Accordingly, the currents flowing through the first BJT Q₁ and the second BJT Q₂ are the same. In such case, the voltage difference between the emitting terminal of the first BJT Q₁ and the second BJT Q₂ is V_(T) ln X, wherein V_(T) is a thermal voltage and equals to

$\frac{KT}{q},$

q is a Coulomb charge, K is Boltzmann's constant and T is a temperature. Thus, the voltage difference between two terminals for the first resistor R₁ is V_(T) ln X.

In view of above-mentioned concept, the first current I₁ is

${\frac{V_{T}\ln \; X}{R_{1}} + \frac{V_{{EB}\; 2}}{R_{2}}},$

wherein V_(EB2) is a voltage difference between a basic terminal and an emitting terminal of the second BJT Q₂. The third current I₃ also equals to

${\frac{V_{T}\ln \; X}{R_{1}} + \frac{V_{{EB}\; 2}}{R_{2}}},$

since the first current I₁ equals to the second current I₂, and the second current I₂ equals to the third current I₃. Therefore, the reference voltage V_(r) equals

$\left. {\frac{V_{T}\ln \; X}{R_{1}} + \frac{V_{{EB}\; 2}}{R_{2}}} \right\rbrack {R_{r}.}$

Ideally, V_(T) has a positive correlation with the temperature variation, and V_(EB2) has a negative correlation with the temperature variation, such that the variation for the voltages counteracts with each other. By this way, the reference voltage Vr can be kept at a constant value regardless of the temperature variation. As above-mentioned, the first voltage V₁ and the second voltage V₂ affects V_(DS) for the transistor in the differential operational amplifier due the temperature variation. Therefore, the stability for the reference voltage V_(r) if no above-mentioned calibration is performed.

FIG. 9 is a schematic diagram illustrating a comparison between the bandgap reference voltage generating circuit of the present invention and the bandgap reference voltage generating circuit for prior art. As shown in FIG. 9, the reference voltage for the prior art significantly changes corresponding to the temperature, therefore the reference voltage provided by the present invention is more stable.

In view of above-mentioned description, the present invention adjusts the first and the second input voltages via at least one adjusting amount changing corresponding to the temperature variation. Thereby the firs input voltage and the second input voltage have less difference corresponding to the temperature variation, thus the suppressing for the V_(DS) of the transistor in the differential operational amplifier decreases. By this way, the differential operational amplifier can have a better performance, and the bandgap reference voltage generating circuit applying the differential operational amplifier can generate a more stable reference voltage.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. 

What is claimed is:
 1. A differential operational amplifier, comprising: a voltage adjusting module, coupled between a first predetermined voltage source and a second predetermined voltage source, for adjusting a first voltage via a first voltage adjusting value to generate a first adjusted voltage, and for adjusting a second voltage via a second voltage adjusting value to generate a second adjusted voltage, wherein the first voltage adjusting value and the second voltage adjusting value change corresponding to a temperature; and a differential signal computing module, coupled between the first predetermined voltage source and the second predetermined voltage source, for generating an output voltage according the first adjusted voltage and the second adjusted voltage.
 2. The differential operational amplifier of claim 1, wherein the voltage adjusting module comprises: a first transistor, comprising: a first terminal coupled to the first predetermined voltage source, a control terminal receiving the first voltage, a second terminal outputting the first adjusted voltage, wherein the first voltage adjusting value is a voltage difference between the control terminal of the first transistor and the second terminal of the first transistor; and a second transistor, comprising: a first terminal coupled to the first predetermined voltage source, a control terminal receiving the second voltage, a second terminal outputting the second adjusted voltage, wherein the first voltage adjusting value is a voltage difference between the control terminal of the first transistor and the second terminal of the first transistor.
 3. The differential operational amplifier of claim 2, wherein the first transistor is a first NMOSFET, wherein the first terminal of the first transistor is a drain terminal, the control terminal of the first transistor is a gate terminal, and the second terminal of the first transistor is a source terminal; wherein the second transistor is a second NMOSFET, wherein the first terminal of the second transistor is a drain terminal, the control terminal of the second transistor is agate terminal, and the second terminal of the second transistor is a source terminal.
 4. The differential operational amplifier of claim 3, wherein the voltage adjusting module further comprises: a first native NMOSFET, comprising: a drain terminal coupled to the first predetermined voltage source, a gate terminal coupled to the gate terminal of the first NMOSFET, and a source terminal coupled to the drain terminal of the first NMOSFET; and a second native NMOSFET, comprising: a drain terminal coupled to the first predetermined voltage source, a gate terminal coupled to the gate terminal of the second NMOSFET, and a source terminal coupled to the drain terminal of the second NMOSFET.
 5. The differential operational amplifier of claim 2, wherein the differential signal operating module comprises: a first PMOSFET, comprising a gate terminal receiving the first adjusted voltage; a second PMOSFET, comprising: a gate terminal receiving the second adjusted voltage, and a source terminal coupled to a source terminal of the first PMOSFET; a third PMOSFET, comprising: a source terminal receiving the first adjusted voltage, and a drain terminal coupled to the source terminal of the first PMOSFET and the second PMOSFET; a fourth PMOSFET, comprising: a source terminal coupled to the first predetermined voltage source, a gate terminal coupled to the gate terminal of the third PMOSFET, and a drain terminal coupled to the gate terminal of the third PMOSFET and an output terminal; a third NMOSFET, comprising: a drain terminal coupled to the drain terminal of the second PMOSFET and a gate terminal of the third NMOSFET, and a source terminal coupled to the second predetermined voltage source; a fourth NMOSFET, comprising: a drain terminal coupled to the drain terminal of the first PMOSFET, a source terminal coupled to the second predetermined voltage source, and a gate terminal coupled to a base of the third NMOSFET; a fifth NMOSFET, comprising: a drain terminal coupled to the output terminal, a gate terminal coupled to the drain terminal of the fourth NMOSFET, and a source terminal coupled to the second predetermined voltage source.
 6. The differential operational amplifier of claim 5, wherein the differential signal computing module comprises: a third native NMOSFET, comprising: a drain terminal coupled to the drain terminal of the fourth PMOSFET, a gate terminal coupled to the gate terminal of the fifth NMOSFET, and a source terminal coupled to the drain terminal of the fifth NMOSFET.
 7. The differential operational amplifier of claim 6, further comprising: a sixth NMOSFET, comprising: a drain terminal coupled to the source terminal of the first NMOSFET, and a source terminal coupled to the second voltage source; and a seventh NMOSFET, comprising: a drain terminal coupled to the source terminal of the second NMOSFET, a source terminal coupled to second predetermined voltage source, and a base coupled to agate terminal of the sixth NMOSFET.
 8. The differential operational amplifier of claim 7, further comprising: a fifth PMOSFET, comprising: a source terminal coupled to the first predetermined voltage source, a gate terminal coupled to a base of the fourth PMOSFET; and an eighth NMOSFET, comprising: a drain terminal coupled to a drain terminal of the fifth PMOSFET and a gate terminal of the eighth NMOSFET, a source terminal coupled to the second predetermined voltage source.
 9. A bandgap reference voltage generating circuit, comprising: a current mirror, for generating a first current at a first current output terminal, for generating a second current at a second current output terminal, and for generating a third current at a third current output terminal, wherein the second current maps from the first current and the third current maps from the first current or the second current; a differential operational amplifier, comprising: an operational output terminal; a first operational input terminal; a second operational input terminal; a voltage adjusting module, coupled between a first predetermined voltage source and a second predetermined voltage source, for adjusting a first voltage via a first voltage adjusting value to generate a first adjusted voltage, and for adjusting a second voltage via a second voltage adjusting value to generate a second adjusted voltage, wherein the first voltage adjusting value and the second voltage adjusting value change corresponding to a temperature; and a differential signal computing module, coupled between the first predetermined voltage source and the second predetermined voltage source, for generating a control voltage according the first adjusted voltage and the second adjusted voltage; a voltage generating module, for generating a first voltage at the first operational input terminal according to the first current, and for generating a second voltage at the second operational input terminal according to the second current, wherein the differential operational amplifier generates the control signal to the current mirror according to the first voltage and the second voltage, to control the first current, the second current and the third current; and a reference voltage resistance device, comprising a first terminal receiving the third current and a second terminal coupled to the second voltage source, wherein the third current generates a reference voltage at the first terminal of the reference voltage resistance device.
 10. The bandgap reference voltage generating circuit of claim 9, wherein the voltage adjusting module comprises: a first transistor, comprising: a first terminal coupled to the first predetermined voltage source, a control terminal receiving the first voltage, a second terminal outputting the first adjusted voltage, wherein the first voltage adjusting value is a voltage difference between the control terminal of the first transistor and the second terminal of the first transistor; and a second transistor, comprising: a first terminal coupled to the first predetermined voltage source, a control terminal receiving the second voltage, a second terminal outputting the second adjusted voltage, wherein the first voltage adjusting value is a voltage difference between the control terminal of the first transistor and the second terminal of the first transistor.
 11. The bandgap reference voltage generating circuit of claim 10, wherein the first transistor is a first NMOSFET, wherein the first terminal of the first transistor is a drain terminal, the control terminal of the first transistor is a gate terminal, and the second terminal of the first transistor is a source terminal; wherein the second transistor is a second NMOSFET, wherein the first terminal of the second transistor is a drain terminal, the control terminal of the second transistor is agate terminal, and the second terminal of the second transistor is a source terminal.
 12. The bandgap reference voltage generating circuit of claim 11, wherein the voltage adjusting module further comprises: a first native NMOSFET, comprising: a drain terminal coupled to the first predetermined voltage source, a gate terminal coupled to the gate terminal of the first NMOSFET, and a source terminal coupled to the drain terminal of the first NMOSFET; and a second native NMOSFET, comprising: a drain terminal coupled to the first predetermined voltage source, a gate terminal coupled to the gate terminal of the second NMOSFET, and a source terminal coupled to the drain terminal of the second NMOSFET.
 13. The bandgap reference voltage generating circuit of claim 10, wherein the differential signal operating module comprises: a first PMOSFET, comprising a gate terminal receiving the first adjusted voltage; a second PMOSFET, comprising: a gate terminal receiving the second adjusted voltage, and a source terminal coupled to a source terminal of the first PMOSFET; a third PMOSFET, comprising: a source terminal receiving the first adjusted voltage, and a drain terminal coupled to the source terminal of the first PMOSFET and the second PMOSFET; a fourth PMOSFET, comprising: a source terminal coupled to the first predetermined voltage source, a gate terminal coupled to the gate terminal of the third PMOSFET, and a drain terminal coupled to the gate terminal of the third PMOSFET and an output terminal; a third NMOSFET, comprising: a drain terminal coupled to the drain terminal of the second PMOSFET and a gate terminal of the third NMOSFET, and a source terminal coupled to the second predetermined voltage source; a fourth NMOSFET, comprising: a drain terminal coupled to the drain terminal of the first PMOSFET, a source terminal coupled to the second predetermined voltage source, and a gate terminal coupled to a base of the third NMOSFET; a fifth NMOSFET, comprising: a drain terminal coupled to the output terminal, a gate terminal coupled to the drain terminal of the fourth NMOSFET, and a source terminal coupled to the second predetermined voltage source.
 14. The bandgap reference voltage generating circuit of claim 13, wherein the differential signal computing module comprises: a third native NMOSFET, comprising: a drain terminal coupled to the drain terminal of the fourth PMOSFET, a gate terminal coupled to the gate terminal of the fifth NMOSFET, and a source terminal coupled to the drain terminal of the fifth NMOSFET.
 15. The bandgap reference voltage generating circuit of claim 14, further comprising: a sixth NMOSFET, comprising: a drain terminal coupled to the source terminal of the first NMOSFET, and a source terminal coupled to the second voltage source; and a seventh NMOSFET, comprising: a drain terminal coupled to the source terminal of the second NMOSFET, a source terminal coupled to second predetermined voltage source, and a base coupled to agate terminal of the sixth NMOSFET.
 16. The bandgap reference voltage generating circuit of claim 15, further comprising: a fifth PMOSFET, comprising: a source terminal coupled to the first predetermined voltage source, a gate terminal coupled to a base of the fourth PMOSFET; and an eighth NMOSFET, comprising: a drain terminal coupled to a source terminal of the fifth PMOSFET and a gate terminal of the eighth NMOSFET, a source terminal coupled to the second predetermined voltage source. 